In recent years, as a method of performing digital signal processing for radio communication, software-defined radio has been attracting attention. Software-defined radio is configured by a reconfigurable circuit (hereinafter, referred to as a “reconfigurable-type circuit”), or a circuit in which a processing content can be changed by a program, or the like.
Patent Literature (hereinafter, referred to as “PTL”) discloses a software-defined radio apparatus of the related art, for example. FIG. 1 is a diagram showing the configuration of the software-defined radio apparatus described in PTL 1. In FIG. 1, software-defined radio apparatus 10 includes antenna 11, radio transmission/reception device 12, resource controller 13, signal processing device (resource) 14, storage apparatus 15, and system controller 16.
Resource controller 13 controls signal processing device (resource) 14 so as to easily realize handover control between different communication systems. Specifically, resource controller 13 manages usable circuit resources among signal processing circuits in signal processing device (resource) 14, the timing (or period), and the like. As resource management method, PTL 1 describes a method which assigns arithmetic processing to a plurality of circuit resources taking into consideration a required arithmetic operation amount per section time necessary for a function to be processed and processing performance in the resources of the signal processing circuits.
In addition, PTL 2 discloses a method for operating a terminal capable of supporting different communication systems (e.g., a satellite communication system and a cellular radio communication system) each being put into autonomous operation and for establishing simultaneous links between the terminal and a plurality of communication systems, for example. The terminal described in PTL 2 checks whether or not a resource can be shared between different communication systems, and shares the resource when the resource can be shared. Specifically, the terminal checks whether or not it is the period during which the resource can be shared according to the priority for link establishment, shares the resource if there is no problem, and connects to a link having low priority, for communication.
An example of a reconfigurable-type circuit or a programmable circuit to be applied to software-defined radio is disclosed in NPL 1. NPL 1 describes a technique (coarse grain reconfigurable technique) which realizes various functions by changing a connection configuration of a plurality of arithmetic units or a processing content of an individual arithmetic unit.
In order to realize more efficient processing, NPL discloses a multithreading technique which divides a program to be processed into a plurality of threads and performs arithmetic operations in a plurality of regions simultaneously in parallel. In the multithreading technique, a plurality of different radio communication systems operated asynchronously or independently are distributed to different threads, whereby simultaneous processing of a plurality of communication systems is made easier. With the effective use of a hardware circuit resource, reduction in size is expected.
PTL 3 discloses an example of software-defined radio taking into consideration the processing time required for a communication system. Specifically, in PTL 3, a DVS (Dynamic Voltage Scaling) or DVFS (Dynamic Voltage and Frequency Scaling) technique is applied to software-defined radio. According to software-defined radio described in PTL 3, the voltage and the clock frequency of an arithmetic processing circuit are controlled such that the conditions for completing processing in the processing time required for the communication system (hereinafter, referred to as allowable processing time) are satisfied. According to software-defined radio described in PTL 3, concurrently with the control described above, the voltage and the clock frequency of an arithmetic processing circuit are controlled such that power consumption is minimized. Specifically, the control method increases or decreases the voltage and the clock frequency as necessary according to the correspondence between the average number of processing cycles required at the time of previous processing, the processing time required at the time of actual processing, and the allowable processing time which is specified according to the communication scheme.
As an example of a requirements specification providing limited processing time, a wireless LAN (Local Area Network) compliant with the IEEE 802.11 standard specification can be cited in a wireless LAN using a CSMA/CA (Carrier Sense Multiple Access/Collision Avoidance) scheme, the allowable processing time is especially short. Specifically, according to this specification, a reception-side terminal performs error detection and determines whether or not there is an error. When determining that there is no error, the reception-side terminal is defined to reply with an acknowledgement (Ack) signal after a predetermined time interval (SIFS: Short inter Frame Space) passes after the completion of reception. For this reason, a sufficient hardware circuit resource is required such that real-time processing is completed in a predetermined period of time.